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# Tutor profile: Teja K.

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Teja K.
Subject Expert and Tutor in Chegg for 4 years, newbie to TutorMe
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## Questions

### Subject:Pre-Algebra

TutorMe
Question:

a) Solve for x- 3x=5x-14 b) Solve for x and y 3x+2y=12 2x-3y=1

Inactive
Teja K.

a) 3x=5x-14 5x-3x=14 2x=14 x=7 b) 3x+2y=12 2x-3y=1 So, 6x+4y=24 and 6x-9y=3 (Multiply equations by 2 and 3 respectively) Subtracting gives y=21/13 x=38/13

### Subject:Electrical Engineering

TutorMe
Question:

a) Assuming minimum length transistors calculate the ration of the width of PMOS and NMOS in a static CMOS inverter that produces an output voltage of 2.2 V for an input voltage of 1.2V. b) In static CMOS inverter if the rise time and fall time of the input signal increases, then which component of the power consumption changes and why? c) Justify the statement βThe switching power consumption at the output node of a pass transistor logic is low in comparison to static CMOS familyβ. d) If a design engineer wants to selectively eliminate the body effect for PMOS in a given circuit, what exactly does he/she mean from the fabrication perspective?

Inactive
Teja K.

a) For the given conditions the PMOS is in linear region of operation while the NMOS is in saturation region of operation. So equating the currents through them πβπ π‘πππππππ π£πππ‘ππππ  πππ ππππ πππ πππ· = 3.0 β 2.2, πππΊ = 3.0 β 1.2 Solution: So for PMOS (0.8 < 1.8-0.8) is in Linear region πβπ π‘πππππππ π£πππ‘ππππ  πππ ππππ πππ ππΊπ = 1.2 β 0, ππ·π = 2.2 β 0 So NMOS (2.2>0.6) is in Saturation region Equating the currents through PMOS and NMOS 50 Γ ππ(2(1.8 β 0.8)0.8 β 0.8^2) = 150 Γ ππ(1.2 β 0.6)^2 ππ = 1.125*ππ b) When the rise time/ fall time of the input signal increases the duration for which both the PMOS and NMOS are simultaneously ON increase as a result the short circuit power consumption increases. c) In pass-transistor logic family the output voltage swing is reduced, since the output node canβt reach rail to rail (0 to VDD- VTN for NMOS and |VTP| to VDD in PMOS) as a result the switching power reduces. d) Yes, it is possible to eliminate body effect in PMOS by ting the source of each PMOS to its body. This is possible in the n-well process where each PMOS has its own well. This comes at the expense of increased area since the minimum well to well spacing rules apply.

### Subject:C Programming

TutorMe
Question:

Give the output of the following programs. Assume that necessary header files are already included. a) int main(){ int m[] = {1,2,3,4,5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; int x, y ; for(x = 0; x < 15; x++){ for ( y = 2; y < m[x]; y++) { if((m[x]%y ==0)) { break; } } if (y == m[x]) { printf("%d ",m[x]); } } return (0); b) int main(){ int one = 1, two = 2; float three = 3.5; printf(" one = %d,two = %d,three = %f \n", one, two, three); { int one = 10; int two = 20; printf(" one = %d,two = %d,three = %f\n", one, two, three); { int three = 100.95; printf(" one = %d,two = %d,three =%d\n", one, two, (int)three); } } return 0; c) int main (void) { int a=9, b=5; int n,m,p=1; n = a - ++b; m = a-- + b--; p *= b + 5; printf ("n = %d m = %d p = %d",n,m,p); return (0); }

Inactive
Teja K.

a) 2 3 5 7 11 13 OR Prime numbers in array. b) one = 1,two = 2,three = 3.500000 one = 10,two = 20,three = 3.500000 one = 10,two = 20,three =100 Instead of 3.500000, student may write 3.5 also. c) n = 3 m = 15 p = 10

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